frameBuffer24BitTft480800=(U32 (*)[SCR_XSIZE_TFT_480800])LCDFRAMEBUFFER;
	rLCDCON1=(CLKVAL_TFT_480800<<8)|(MVAL_USED<<7)|(3<<5)|(13<<1)|0;
		// TFT LCD panel,24bpp TFT,ENVID=off
	rLCDCON2=(VBPD_480800<<24)|(LINEVAL_TFT_480800<<14)|(VFPD_480800<<6)|(VSPW_480800);
	rLCDCON3=(HBPD_480800<<19)|(HOZVAL_TFT_480800<<8)|(HFPD_480800);
	rLCDCON4=(MVAL<<8)|(HSPW_480800);
	rLCDCON5=(1<<12)|(1<<11)|(1<<10)|(0<<9)|(0<<8)|(0<<7)|(0<<1);	//FRM5:6:5,HSYNC and VSYNC are inverted (and pwren signal enable)
	rLCDSADDR1=(((U32)frameBuffer24BitTft480800>>22)<<21)|M5D((U32)frameBuffer24BitTft480800>>1);
	rLCDSADDR2=M5D( ((U32)frameBuffer24BitTft480800+(SCR_XSIZE_TFT_480800*LCD_YSIZE_TFT_480800*4))>>1 );
	rLCDSADDR3=(((SCR_XSIZE_TFT_480800-LCD_XSIZE_TFT_480800)*2)<<11)|(LCD_XSIZE_TFT_480800*2);
	rLCDINTMSK|=(3); // MASK LCD Sub Interrupt
	rLPCSEL&=(~7); // Disable LPC3600
	rTPAL=0; // Disable Temp Palette